`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/09/14 21:22:21
// Design Name: 
// Module Name: WritebackAddress
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

`include "funct.v"
`include "opcode.v"

module WritebackAddress(
//    input wire [31:0] i_rs_out,
//    input wire [31:0] i_rt_out,
//    input wire [31:0] i_inst_addr,
    input wire [31:0] i_inst,
//    input wire [31:0] i_imm32_zero,
//    input wire [31:0] i_imm32_sign,
    
    output wire [4:0] o_result
    );
    
    wire [5:0] op;
    wire [5:0] funct;
    wire [4:0] rs;
    wire [4:0] rt;
    wire [4:0] rd;
    assign op = i_inst[31:26];
    assign funct = i_inst[5:0];
    assign rs = i_inst[25:21];
    assign rt = i_inst[20:16];
    assign rd = i_inst[15:11];
    
//    wire [4:0] special_result;
//    assign special_result
//        = funct == `FUNCT_ADD ? rd
//        : 0;
    
    assign o_result
        = op == `OP_SPECIAL ? rd
        : op == `OP_SPECIAL2 ? rd
        : op == `OP_REGIMM ? 5'b11111
        : op == `OP_JAL ? 5'b11111
        : rt;
    
endmodule
